1. Field of the Invention
The present invention relates to a semiconductor device having an active operation mode wherein a large amount of current is consumed and a standby operation mode wherein a very small amount of current is consumed, and more particularly to a semiconductor device driven by a low voltage.
2. Description of the Related Art
Recently, as a DRAM or an LSI has been highly integrated and power consumption of a semiconductor device has been reduced to allow battery driving, an internal source voltage (hereinafter referred to simply as "first voltage") V.sub.CC has become lower and lower. As apparent from, FIG. 1A, the internal source voltage against generation of DRAM has becomes lower. For example, in a 1 G or 4 G-bit DRAM, the first voltage V.sub.CC is reduced as low as 1.5 V to 1.0 V. A battery-driven LSI is required to be driven at a voltage as low as 1.5 V to 0.8 V.
However, since in an LSI a MOS transistor has a threshold voltage V.sub.T, operation speed or gate delay time is suddenly reduced, when the first voltage V.sub.CC is increased near the threshold voltage V.sub.T. This phenomenon is shown in FIG. 1B. If the threshold voltage is lowered to prevent the sudden reduction of gate delay time, a standby current is greatly increased.
FIG. 2 shows a part of circuit in a memory according to the conventional art; and shows three stage inverter circuits. With the circuit of FIG. 2, in a standby state, nodes N.sub.1 and N.sub.3 are set at an "L" level and nodes N.sub.2 and N.sub.4 are set at an "H" level. In this standby state, a leak current I leak flows on the two inverters of the former stages via transistors Q.sub.1 and Q.sub.4. Since this phenomenon occurs throughout the memory, the leak current is greatly increased when the threshold voltage of the transistors is low.
FIG. 1C is a diagram showing the relationship between the threshold voltage V.sub.T of a transistor and the standby current of a 16M bit DRAM level chip. According to FIG. 1C, a threshold voltage of at least 0.6 V is required to suppress the standby current to 1 .mu.A.
FIGS. 3A and 3B show the change of the current flowing through a SRAM and a DRAM in the active state and the standby state. In FIGS. 3A and 3B, a current in the active state is indicated as I.sub.CC1 and a current in the standby state is indicated as I.sub.CC2. Normally, the memory is set in the standby state, when data is not accessed, in order to reduce the current flowing therein. However, since the standby period is much longer than the active period, it is necessary to reduce the current I.sub.CC2 in the standby state to a sufficiently low level. The standby state determines the current flowing through a memory when the memory is not operated by a battery backup.
As described above, in a conventional semiconductor device, when the first voltage V.sub.CC of an LSI is lowered, the operation speed or gate delay time is lowered as the first voltage V.sub.CC approaches the threshold voltage V.sub.T. And when the threshold voltage V.sub.T is lowered, the standby current is increased.